Optimizing Energy to Minimize Errors in Approximate Ripple Carry Adders

We present a theoretical foundation and a methodology for automatically assigning supply voltages to approximate ripple carry adders in which accuracy is traded for energy consumption. The error minimization problem for a fixed energy budget is formulated as a binned geometric program. We first use geometric programming to minimize the average error of the adder and compute the supply voltages at the gate level, after which we bin the voltages to a finite set (of four or five voltages) using a heuristic. Using HSPICE in 90nm technology, we show simulation results by applying our methodology to a ripple carry adder and obtain savings of up to 2:58X (and by a median of 1:58X) in average error, when compared to uniform voltage scaling, for the same energy consumption. Compared to a naive biased voltage scaling (n-BIVOS), which is the best prior art in literature, a Binned Geometric Program Solution (BGPS) as proposed in this paper saves 32.3% energy with the same PSNR in an 8point FFT example or, alternatively, increases the PSNR by 8.5db for the same energy consumption for the FFT.